6809/6309 Registers

     _________________________________________________________________________
    | X  - 16 bit index register                                              |
    | Y  - 16 bit index register                                              |
    | U  - 16 bit user-stack pointer                                          |
    | S  - 16 bit system-stack pointer                                        |
    | PC - 16 bit program counter register                                    |
    |*V  - 16 bit variable register (inter-register instructions only)        |
    |*0  - 8/16 bit zero register   (inter-register instructions only)        |
    |-------------------------------------------------------------------------|
    | A  - 8 bit accumulator             |                                    |
    | B  - 8 bit accumulator             |    Accumulator structure map:      |
    |*E  - 8 bit accumulator             |      ----- ----- ----- -----       |
    |*F  - 8 bit accumulator             |     |  A  |  B  |  E  |  F  |      |
    | D  - 16 bit concatenated reg.(A B) |      -----------+-----------       |
    |*W  - 16 bit concatenated reg.(E F) |     |     D     |     W     |      |
    |*Q  - 32 bit concatenated reg.(D W) |      -----------------------       |
    |------------------------------------|     |           Q           |      |
    |*MD - 8 bit mode/error register     |      -----------------------       |
    | CC - 8 bit condition code register | bit  31   24    15    8     0      |
    | DP - 8 bit direct page register    |                                    |
     -------------------------------------------------------------------------
      * Indicates new registers in 6309 CPU.

                             Push/Pull Order of Stack

             Pull order                  Push/Pull Post byte
                 |                 ------------------------------- 
                \|/               | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
                 '                 -------------------------------
                 CC                 |   |   |   |   |   |   |   |____CCr
                 A\                 |   |   |   |   |   |   |________A
                 B/ D\ Q            |   |   |   |   |   |____________B
                 E\ W/              |   |   |   |   |________________DPr
                 F/                 |   |   |   |____________________X
                 DP                 |   |   |________________________Y
                X-hi                |   |____________________________S/U
                X-low               |________________________________PC
                Y-hi       
                Y-low    
                U/S-hi                                                
                U/S-low
                PC-hi
                PC-low
                  .
                 /|\
                  |
              Push order

                                       Condition Code Register
                                  ------------------------------- 
                                 | E | F | H | I | N | Z | V | C |
                                  -------------------------------
                    Entire flag____|   |   |   |   |   |   |   |____Carry flag
                      FIRQ mask________|   |   |   |   |   |________Overflow
                     Half carry____________|   |   |   |____________Zero
                       IRQ mask________________|   |________________Negative

       The PSH(s,u) and PUL(s,u) instructions require one additional
       cycle for each byte pushed or pulled.

    From:   HD63B09EP Technical Reference Guide
            By Chet Simpson and Alan DeKok